JEDEC Updates DDR5 Specification for Increased Security Against Rowhammer Attacks, New DDR5-8800 Reference Speed

JEDEC Solid State Technology Association announced publication of the JESD79-5C DDR5 SDRAM standard. This important update to the JEDEC DDR5 SDRAM standard includes features designed to improve reliability and security and enhance performance in a wide range of applications from high-performance servers to emerging technologies such as AI and machine learning. 

JESD79-5C introduces an innovative solution to improve DRAM data integrity called Per-Row Activation Counting (PRAC). PRAC precisely counts DRAM activations on a wordline granularity. When PRAC-enabled DRAM detects an excessive number of activations, it alerts the system to pause traffic and to designate time for mitigative measures. These interrelated actions underpin PRAC's ability to provide a fundamentally accurate and predictable approach for addressing data integrity challenges through close coordination between the DRAM and the system.

Additional features offered in JESD79-5C DDR5 include:

Expansion of timing parameters definition from 6800 Mbps to 8800 Mbps

Inclusion of DRAM core timings and Tx/Rx AC timings extended up to 8800 Mbps, compared to the previous version which supported only up to 6400 timing parameters and partial pieces up to 7200 DRAM core timings

Introduction of Self-Refresh Exit Clock Sync for I/O Training Optimization

Incorporation of DDP (Dual-Die Package) timings

Deprecation of PASR (Partial Array Self Refresh) to address security concerns