JEDEC Adds Two New Standards Supporting CXL Technology

JEDEC Solid State Technology Association announced the publication of two new standards supporting Compute Express Link (CXL ) technology. These additions complete a comprehensive family of four standards that provide the industry with unparalleled flexibility to develop a wide range of CXL memory products. 

JESD319: JEDEC Memory Controller Standard - for Compute Express Link (CXL ) defines the overall specifications, interface parameters, signaling protocols, and features for a CXL Memory Controller ASIC. Key aspects include pinout reference information and a functional description that includes CXL interface, memory controller, memory RAS, metadata, clocking, reset, performance, and controller configuration requirements. JESD319 focuses on the CXL 3.1 based direct attached memory expansion application, providing a baseline of standardized functionality while allowing for additional innovations and customizations.

JESD325: JEDEC Memory Device Management Standard - for Compute Express Link (CXL ) provides a reference specification for systems and device management capabilities found in CXL memory devices. It targets field-replaceable CXL memory devices based on PCIe Gen 5 and is compliant with the CXL 2.0 Specification or later. Key topics covered include:

Management Interface Requirements (Physical layer, Transport Layer, and Protocol Layer)
Security Requirements (Signature and Hashing Algorithms, Secure Boot, Secure FW Update, SPDM)
Requirements for Management Sensors and Controls
Thermal Management Requirements
FRU Vital Product Data content requirements

JESD319 and JESD325 join JEDEC's previously published standards on this topic: JESD317A: JEDEC Memory Module Reference Base Standard - for Compute Express Link (CXL ) and JESD405-1B: JEDEC Memory Module Label - for Compute Express Link (CXL ).