Samsung unveils DRAM technology smaller than 10nm

Samsung and Samsung Advanced Institute of Technology on Tuesday unveiled its technology to make DRAM smaller than 10-nanometer (nm).

The memory cells are stacked on the periphery circuits, a method shortened as cell-on-peri (CoP), according to the tech giant’s announcement during the 70th International Electron Devices Meeting hosted by IEEE and held in San Francisco. IEEE, or the Institute of Electrical and Electronics Engineers, is the preeminent professional organization for electrical engineering.

This is as opposed to the current way where the peri transistor were placed below the memory cell and were prone to be damaged during the high-temperature stacking process, causing performance degradation.

Samsung has dubbed its technology “High Heat Resistant Amorphous Oxide Semiconductor Transistor for Sub-10nm CoP Vertical Channel DRAM Transistors.”

An amorphous indium gallium oxide (InGaO)-based transistor is used, which can resist up to 550 degrees Celsius of heat, to prevent performance degradation the South Korean tech giant claimed. 

The vertical channel transistor has a channel length of 100nm and can be integrated with a monolithic CoP DRAM architecture, Samsung added.

During testing, the drain current saw minimal deterioration and the transistor performed well during aging tests as well, the company noted.

Sources said the technology however was still at the research stage and will be applied in 0a and 0b class DRAMs that are sub-10nm in the future.