According to public information, Samsung Electronics recently filed a new patent for High Bandwidth Memory (HBM) packaging, aiming to address the reliability challenges faced by high-stack products such as HBM4E and HBM5. As the number of stacked layers in HBM continues to increase, the patent proposes a structural optimization scheme for the top "Dummy Die," intending to enhance the mechanical stability and production yield of the packaging.
Yield Challenges Brought by High Stacking
In the current standard HBM structure, multiple memory dies are vertically stacked on a base die, typically covered by a top dummy die to meet packaging height specifications and provide mechanical protection and heat dissipation. However, as the number of stacked layers increases from the conventional 8 to 12, and even exceeds 16, the top dummy die becomes prone to issues such as wafer warpage, delamination, and cracking. Data indicates that as the number of layers increases, the relevant yield drops by 10% to 20%, and can even plummet to 40%–60% when exceeding 16 layers.
"Inverted Pyramid" Structure and Deep Groove Sawing Process
To mitigate these issues, Samsung proposes an innovative structural design in this patent. The new scheme shapes the top dummy die into an "inverted pyramid" form that narrows at the bottom and widens at the top, featuring a composite structure of three-tiered steps and curved surfaces on its sides. In terms of manufacturing, the patent introduces "Deep Groove Sawing" technology. Compared to traditional mechanical blade sawing, this laser-based process can cut deeper and more precise grooves, enhancing the mechanical strength of the die while effectively minimizing damage to the semiconductor crystal structure.
Interface Optimization and Thermal Management Design
Beyond macro-structural adjustments, the patent also incorporates targeted designs at the microscopic interface and for thermal management. In the Non-Bond Region (NBR), Samsung pre-forms trench structures to prevent debris generated during the sawing process from contaminating the bonding interface, thereby enhancing the reliability of fusion bonding. Regarding heat dissipation, the patent precisely controls the vertical distance between the bottom surface of the bonding insulating layer and the horizontal extension surface to 1–10 micrometers, maintaining current heat transfer efficiency. Additionally, it optimizes the protruding surface structure to reduce the volume of the Epoxy Molding Compound (EMC), which is expected to further improve the overall heat transfer path.
Technology Integration and Industry Outlook
Industry analysts point out that with the rising demand for AI computing power, HBM5 products with over 16 layers will become a crucial future development direction, and the physical bottlenecks caused by high stacking are thresholds that all manufacturers must cross. Samsung’s newly filed patent, combined with its existing hybrid bonding and Heat Path Block (HPB) technologies, demonstrates its attempt to build comprehensive competitiveness through multi-dimensional packaging innovations. However, from patent filing to ultimate mass production, the related technologies still need to undergo rigorous customer validation and yield ramp-up cycles.
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