Samsung Plans to Adopt 2nm Process for Custom HBM Logic Chips

According to South Korean media reports, Samsung Electronics will continue its "process advantage" strategy for custom HBM memory, offering a series of base die solutions ranging from 4nm down to the current most advanced 2nm technology. In comparison, TSMC plans to adopt the N3P process (second-generation 3nm technology) for custom HBM base dies.

HBM consists of core dies and a logic die. Core dies comprise multiple vertically stacked and interconnected DRAM dies, while the logic die sits below them, handling controller functions. The logic die connects the HBM to the system semiconductor's PHY (Physical Layer), such as a GPU, enabling high-speed data exchange.

As HBM technology matures, the processes applied to logic dies are also advancing rapidly. For instance, starting with HBM4, which is set for full-scale production this year, logic dies will be manufactured using foundry processes rather than traditional DRAM processes. This shift is due to the advantages foundry processes offer in terms of performance and energy efficiency compared to DRAM processes.

Samsung Electronics employs a 4nm process for HBM4 logic dies. The chip development and mass production are handled by the System LSI division and the Foundry division within the Device Solutions (DS) business unit. Furthermore, Samsung has been confirmed to be designing logic chips for custom HBM using a 2nm process.

Custom HBM refers to HBM where customers integrate their required functionalities into the logic die. This customization is expected to become widely adopted starting with HBM4E (the seventh-generation HBM). HBM4E is anticipated to be released next year.