JEDEC Previews LPDDR6 Roadmap Expanding LPDDR into Data Centers and Processing-in-Memory

JEDEC previewed a set of new features planned for incorporation into the next version of its JESD209‑6 LPDDR6 standard. It has been working to enhance the next version of the standard to extend LPDDR6 beyond mobile platforms to support selected data center and accelerated computing workloads. 

Planned features for the upcoming LPDDR6 update include:
(1) Narrower per-die interface (x6) enables higher capacities: With the move to a non-binary interface width – from x16 to x24, the inclusion of x12 and an additional x6 sub-channel mode, allows more die per package and higher memory capacities per component and per channel, a critical enabler for AI-scale memory footprints.

(2) Flexible metadata carve‑out intended to minimize impact to peak data throughput, giving data center customers the option to balance user capacity and metadata needs according to their specific reliability requirements.

(3) 512 GB density on the horizon: LPDDR6 is expected to unlock densities beyond the current LPDDR5/5X maximum, a capability designed to address the ever-growing memory capacity requirements of AI training and inference workloads.

(4) LPDDR6 SOCAMM2 module standard in development. 

JEDEC is also nearing completion of a standard for LPDDR6 Processing‑in‑Memory (LPDDR6 PIM) technology, which complements the broader LPDDR6 roadmap, a next‑generation memory solution intended to address the rapidly increasing performance and energy‑efficiency requirements of edge and data‑center inference workloads.